The present invention relates to semiconductor integrated circuit devices, and more particularly, to a technique effectively applied to a semiconductor integrated circuit device having a plurality of metal insulator semiconductor field effect transistors (MISFETs) microfabricated.
Conventionally, the layout design of a semiconductor integrated circuit device includes extending a diffusion layer for power supply in one direction, and arranging a metal oxide semiconductor (MOS) transistor for forming a desired circuit in the layer, all of which are identified as a cell. One example of such a cell layout is disclosed in, for example, Japanese Unexamined Patent Publication No. 2006-253375 (Patent Document 1). The diffusion layer for power supply formed to extend in one direction is also referred to as a “tap”.
Japanese Unexamined Patent Publication No. 2006-66484 (Patent Document 2) discloses a semiconductor circuit with an excellent anti-radiation property in which one MOS transistor is coupled in series to one or more other MOS transistors with the same node thereby to prevent the failure of the circuit even when any one of the MOS transistors is broken down.    [Patent Document 1]    Japanese Unexamined Patent Publication No. 2006-253375    [Patent Document 2]    Japanese Unexamined Patent Publication No. 2006-66484